An important aspect of an integrated circuit (IC) is the amount of current that the IC draws when in use. The amount of current drawn is directly related to the power consumption of the IC, and so it is desirable to reduce current consumption whenever possible. The current drawn by an IC can include "active" current, consumed when active devices, such as transistors, within the IC are undergoing current or voltage switching operations, and "stand-by" current, consumed when the active devices within the IC are in a quiescent state.
In the case of dynamic random access memories (DRAMs), certain internal circuits can consume considerable amounts of stand-by current; for example, bit line reference (BLR) driver circuits and plate voltage (PLT) driver circuits. A BLR driver circuit provides a BLR voltage to a BLR node. During a read operation, sense amplifiers within the DRAM compare the voltage at the BLR node to voltages on the bit lines to generate a data output signal. The BLR circuit can be an amplifier having the positive input tied to a reference BLR voltage, and the negative input tied to the BLR node. The output of the amplifier is also coupled to the negative input aid the BLR node. In the event the voltage at the BLR node begins to drop below the BLR voltage, the BLR circuit charges the reference node back up to the BLR voltage.
The PLT driver within a DRAM provides a "plate" voltage to a portion, or all, of the storage capacitors within the DRAM array. The plate voltage may vary according to operating mode of the DRAM. For example, in an active mode, the plate voltage may be some voltage intermediate a logic high and logic low voltage, while in an stand-by mode, the plate voltage may be the low power supply voltage. The PLT driver may also be an amplifier circuit having a negative input coupled to a plate node, a positive input coupled to a reference PLT voltage and an output also coupled to the plate node and the negative input. In the event the plate voltage varies from the desired plate voltage, the PLT driver will charge or discharge the plate node and thus return it to the desired plate voltage.
The reason that BLR driver and PLT drivers can consume considerable stand-by current is that such circuits are typically "class A" mode amplifier circuits. Class A mode amplifiers include output drivers that are biased to draw a relatively high current in a quiescent state. One example of the input voltage current response of a class A amplifier is set forth in FIG. 1. The current drawn reaches a high level at a lowest input voltage (VL), and a low level at the highest input voltage (VH). Notably, at the intermediate voltage level (Vmid), the bias current (Ibias) is drawn. Thus, in the event a DRAM is in a stand-by mode, those circuits having a class A mode amplifier configuration will continuously draw a relatively high current, contributing to the overall stand-by current.
A number of approaches have been taken to reduce stand-by current of class A amplifier circuits within a DRAM. A first approach involves utilizing weaker class A amplifier circuits. The biasing current can be reduced, with a corresponding reduction in the size of the output driver devices. A drawback to such an approach is that when an amplifier output node potential varies (a BLR node or PLT node, for example) due to the reduced size of the devices making up the amplifier, it may take too much time to charge or discharge the output node back up to, or down to, the desired reference voltage (the BLR voltage or PLT voltage, for example).
Another approach to reducing the current consumption of DRAM BLR circuits and PLT circuits, is to employ two different circuits, one for stand-by operation and one for active operation. The active devices within the stand-by circuits can be comparatively small, as they would have to account for variations in their outputs that result from leakage, or other such parasitic effects. The devices within the active circuits can be much larger, providing rapid response for the DRAM in the active mode, ensuring any variations in output nodes are quickly compensated for. A drawback to using an active and stand-by circuit is the additional amount of area required for such a solution. Further logic circuits and control lines must be created to turn the circuits on and off depending upon the mode (stand-by or active).
Another type of class A type amplifier circuit is the high-speed input buffers used in some DRAMs. High-speed input buffers receive externally applied signals on a bus line, and amplify (buffer) them for use within the DRAM. After the input signal has been detected, the bus line might be returned to a voltage level intermediate a logic high and logic low level. When the input buffers are class A type circuits, as in the case of the BLR and PLT circuits described above, the input buffers will draw relatively large amounts of current when the bus lines are idle, further contributing to additional stand-by current.
It would be desirable to provide an alternative approach to such class A circuits as the bit line reference circuit, plate voltage circuit, and high speed input buffer circuit described above.